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Research Group Details


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VLSI Research Group (VLR)





About Us


The VLSI Research Group (VLR) of Department of Computer Science and Engineering, University of Dhaka conducts high quality researches on VLSI with the help of dedicated faculties along with talented students and research fellows. The research interests of this group includes VLSI CAD, VLSI design, Electronic System Design, Representations of Logic Functions, Multiple-valued Logic, FPGAs, Computer Architecture, Logic Synthesis and Formal Verification, Reversible Logic Synthesis, etc.

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Faculty

  1. Dr. Hafiz Md. Hasan Babu (2001 - Present)
  2. Dr. Lafifa Jamal (2010 - Present)

Research Fellow

    PhD Student

    1. Lafifa Jamal (2015 - Present)
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    MPhil Student

      MS Student

        BSc Student

          Staff

            Alumni

            Faculty


            1. Dr. Ahsan Raja Chowdhury (2007 - 2010)
            2. Dr. Md. Rafiqul Islam (2001 - 2005)

            MS Student


            1. Jakia Sultana (2008 - 2008)
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            2. Raqibur Rahman (2008 - 2008)
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            3. Nazma Tara (2009 - 2009)
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            4. Tania Ferdaus (2009 - 2009)
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            BSc Student


            1. Naushin Nower (2009 - 2009)
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            1. Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu, Lafifa Jamal, Ashis Kumar Biswas: An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem. IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2017), Bochum, Germany. 116-121 (2017)
            2. Hafiz Md. Hasan Babu, Lafifa Jamal, Sayanton Vhaduri Dibbo, Ashis Kumar Biswas: Area and Delay Efficient Design of a Quantum Bit String Comparator. IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2017), Bochum, Germany. 51-56 (2017)
            3. Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu, Lafifa Jamal: A Cost-Efficient LUT-Based BCD Adder Design. Future Technologies Conference 2017 (FTC 2017), Vancouver, BC, Canada. (2017)
            4. Sayanton Vhaduri Dibbo, Hafiz Md. Hasan Babu, Lafifa Jamal: An Efficient Design Technique of a Quantum Divider Circuit. International Symposium on Circuit and Systems (ISCAS 2016), Montreal, Canada. 2102-2105 (2016)
            5. Sadia Nowrin, Lafifa Jamal, Hafiz Md. Hasan Babu: Design of an Optimized Reversible Bidirectional Barrel Shifter. International Symposium on Circuit and Systems (ISCAS 2016), Montreal, Canada. 730-733 (2016)
            6. Nusrat Jahan Lisa , Hafiz Md. Hasan Babu: A Compact Representation of a Quantum Controlled Ternary Barrel Shifter. 2015 IEEE Int'l Symposium on Circuits & Systems, Lisbon, Portugal. (2015)
            7. Ankur Sarker, Tanvir Ahmed, S. M. Mahbubur Rashid , Hafiz Md. Hasan Babu: Design of Reversible Full Adder Circuit Using DNA. American Journal of Bioinformatics . (2015)
            8. Ankur Sarker, Mohd. Istiaq Sharif, S. M. Mahbubur Rashid , Hafiz Md. Hasan Babu: Implementation of Reversible Multiplier Circuit Using Deoxyribonucleic Acid. 13th IEEE International Conference on Bio Informatics and Bio Engineering (BIBE), Chania, Greece. (2015)
            9. Nusrat Jahan Lisa, Hafiz Md. Hasan Babu: Design of a Compact Reversible Carry Look-Ahead Adder Using Dynamic Programming. 28th International Conference on VLSI Design, Bengaluru, India. (2015)
            10. Ankur Sarker, Hafiz Md. Hasan Babu, S. M. Mahbubur Rashid: Design of a DNA-based Reversible Arithmetic and Logic Unit. IET Nanobiotechnology , UK. (2015)
            11. Lafifa Jamal, Hafiz Md. Hasan Babu: Design and Implementation of a Reversible Central Processing Unit. IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2015), Montpellier, France. (2015)
            12. Nusrat Jahan Lisa, Hafiz Md. Hasan Babu: Design of a Compact Ternary Parallel Adder/Subtractor Circuit in Quantum Computing. IEEE International Symposium on Multiple-Valued Logic (ISMVL 2015), University of Waterloo, Canada. (2015)
            13. Nusrat Jahan Lisa, Hafiz Md. Hasan Babu: A Compact Realization of an n-Bit Quantum Carry Skip Adder Circuit with Optimal Delay. 2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), UK. 270-277 (2014)
            14. Nusrat Jahan Lisa, Hafiz Md. Hasan Babu: Minimization of a Reversible Quantum 2n-to- n BCD Priority Encoder. 10th ACM/IEEE International Symposium on Nanoscale Architectures, Paris, France. 77-82 (2014)
            15. Ankur Sarker, Hafiz Md. Hasan Babu: A Novel Approach to Perform Addition and Subtraction Operation Using DNA. 2014 IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, Australia. (2014)
            16. Hafiz Md. Hasan Babu, Nazir Saleheen, Lafifa Jamal, Sheikh Muhammad Sarwar , Tsutomu Sasao: Approach to design a compact reversible low power binary comparator. IET Computers & Digital Techniques. 8(3): 129-139 (2014)
            17. Lafifa Jamal, Hafiz Md. Hasan Babu, Md. Masbaul Alam: Design of a Compact Reversible Fault Tolerant Field Programmable Gate Array: A Novel Approach in Reversible Logic Synthesis. Elsevier Journal of Sustainable Computing: Informatics and Systems. 3(4): 286-294 (2013)
            18. Nusrat Jahan Lisa, Hafiz Md. Hasan Babu: A Compact Realization of a Reversible Quantum n-to-2n Decoder. 2013 IEEE 4th International Conference on Electronics Information and Emergency Communication, Beijing, China. 102-105 (2013)
            19. Tanvir Ahmed, Ankur Sarker, Mohd. Istiaq Sharif, Md. Atiqur Rahman, S. M. Mahbubur Rashid , Hafiz Md. Hasan Babu: A Novel Approach to Design a Reversible Shifter Circuit Using DNA. 26th IEEE International System-on-Chip Conference (SOCC 2013), Erlangen, Germany. (2013)
            20. Md.Shamsujjoha, Hafiz Md. Hasan Babu, Lafifa Jamal: An Efficient Approach to Design a Reversible Control Unit of a Processor. Elsevier Journal of Microelectronics. 44(6): 519-537 (2013)
            21. Hafiz Md. Hasan Babu, Lafifa Jamal, Nazir Saleheen: An Efficient Approach for Designing a Reversible Fault Tolerant n-Bit Carry Look-Ahead Adder. 26th IEEE International System-on-Chip Conference (SOCC 2013), Erlangen, Germany. 98-103 (2013)
            22. Lafifa Jamal, Hafiz Md. Hasan Babu: Efficient Approaches to Design a Reversible Floating Point Divider. The IEEE International Symposium on Circuits and Systems (ISCAS 2013), Beijing, China. 3004-3007 (2013)
            23. Lafifa Jamal, Md. Mushfiqur Rahman, Hafiz Md. Hasan Babu: An Optimal Design of a Fault Tolerant Reversible Multiplier. 26th IEEE International System-on-Chip Conference (SOCC 2013), Erlangen, Germany. 37-42 (2013)
            24. Md. Shamsujjoha , Hafiz Md. Hasan Babu: A Low Power Fault Tolerant Reversible Decoder Using MOS Transistors. 26th IEEE International Conference on VLSI Design (VLSID 2013), Pune, India. 368-373 (2013)
            25. Hafiz Md. Hasan Babu, Md. Shamsujjoha, Lafifa Jamal , Ahsan Raja Chowdhury: Design of a Fault Tolerant Reversible Compact Unidirectional Barrel Shifter. 26th IEEE International Conference on VLSI Design (VLSID 2013), Pune, India. 103-108 (2013)
            26. Lafifa Jamal, Farah Sharmin, Md. Abdul Mottalib, Hafiz Md. Hasan Babu: Design and Minimization of Reversible Circuits for a Data Acquisition and Storage System. The International Journal of Engineering and Technology. 2(1): 9-15 (2012)
            27. Lafifa Jamal, , Md.Shamsujjoha, Hafiz Md. Hasan Babu: Design of Optimal Reversible Carry Look-Ahead Adder with Optimal Garbage and Quantum Cost. The International Journal of Engineering and Technology. 2(1): 44-50 (2012)
            28. Md. Shamsujjoha, Nazma Tara, Lafifa Jamal, Hafiz Md. Hasan Babu: An Efficient Reversible Fault Tolerant Plessey Logic Block of Field Programable Gate Array. 4th Workshop on Reversible Computation, Copenhagen, Denmark (published in Lecture Notes in Computer Science, Springer). (2012)
            29. Lafifa Jamal, Md. Masbaul Alam, M. A. Mottalib , Hafiz Md. Hasan Babu: On the Compact Designs of Low Power Reversible Decoders and Sequential Circuits. 16th International Symposium on VLSI Design and Test, Shibpur, India, pp. 281-288 (published in Lecture Notes in Computer Science, Springer). (2012)
            30. Sajib Kumar Mitra, Lafifa Jamal, Mineo Kaneko, Hafiz Md. Hasan Babu: An Efficient Approach for Designing and Minimizing Reversible Programmable Logic Arrays. ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), Salt Lake City, Utah, USA. 215-220 (2012)
            31. Naimul Huda, Shahed Anwar, Lafifa Jamal, Hafiz Md. Hasan Babu: Design of a Reversible Random Access Memory. Dhaka University Journal of Applied Science & Engineering. 2(1): 31-38 (2011)
            32. Farah Sharmin, Md. Masbaul Alam Polash, Md. Shamsujjoha, Lafifa Jamal, Hafiz Md. Hasan Babu: Design of a Compact Reversible Random Access Memory. 4th IEEE International Conference on Computer Science and Information Technology, Chengdu, China. 103-107 (2011)
            33. Rubaia Rahman, Lafifa Jamal, Hafiz Md. Hasan Babu: Design of Reversible Fault Tolerant Programmable Logic Arrays with Vector Orientation. International Journal of Information and Communication Technology Research. 1(8): 337-343 (2011)
            34. Ankur Sarker, Tanvir Ahmed, S. M. Mahbubur Rashid, Shahed Anwar, Lafifa Jamal, Nazma Tara, Md. Masbaul Alam, Hafiz Md. Hasan Babu: Realization of Reversible Logic in DNA Computing. IEEE 11th International Conference on Bioinformatics & Bioengineering, Taichung, Taiwan. 261-265 (2011)
            35. Ankur Sarker, Tanvir Ahmed, S.M. Mahbubur Rashid, Shahed Anwar, Hafiz Md. Hasan Babu: New Approach to Design a Reversible Full- Adder Circuit Using Deoxyribonucleic Acid. IEEE 11th International Conference on Bioinformatics & Bioengineering, Taichung, Taiwan . (2011)
            36. Mohammod Akbar Kabir, Hafiz Md. Hasan Babu, Liakot Ali, Lafifa Jamal: Design of a High Performance Low Cost IC Tester - A Conceptual View. Dhaka University Journal of Science. 58(1): 63-66 (2010)
            37. Noor Muhammed Nayeem, Md. Adnan Hossain, Md. Mutasimul Haque, Lafifa Jamal, Hafiz Md. Hasan Babu: Novel Reversible Division Hardware. 52nd IEEE International Midwest Symposium on Circuits and Systems, Cancun, Mexico. 1134-1138 (2009)
            38. Noor Muhammed Nayeem, Lafifa Jamal, Hafiz Md. Hasan Babu: Efficient Reversible Montgomery Multiplier and Its Application to Hardware Cryptography. Journal of Computer Science (Science Publications, USA). 5 (1): 49-56 (2009)
            39. Abu Sadat Md. Sayem, Md. Masbaul Alam Polash, Hafiz Md. Hasan Babu: Design of a Reversible Logic Block of Field Programmable Gate Array. Silver Jubilee Conference on Communication Technologies & VLSI design, VIT University, Vellore, India. 502-503 (2009)
            40. Noor Muhammed Nayeem, Md. Adnan Hossain, Lafifa Jamal, Hafiz Md. Hasan Babu: Efficient Design of Shift Registers Using Reversible Logic. International Conference on Signal Processing, Singapore. 474-478 (2009)
            41. Hafiz Md. Hasan Babu: On the Minimization of Complete Test Set of Reversible K-CNOT Circuits for Stuck at Fault Model. International Conference on Computer and Information Technology (ICCIT 2008), Bangladesh. 7-12 (2008)
            42. Hafiz Md. Hasan Babu: Minimization of CTS of K-CNOT Circuits for SSF and MSF Model. 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, USA. 290-298 (2008)
            43. Ashis Kumar Biswas, Md. Mahmudul Hasan, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu: Efficient Approaches for Designing Reversible Binary Coded Decimal Adders. Elsevier Journal of Microelectronics. vol. 39: 1693–1703 (2008)
            44. Hafiz Md. Hasan Babu: A Novel Approach to Design BCD Adder and Carry Skip BCD Adder. 21th IEEE International Conference on VLSI Design. 566-571 (2008)
            45. Hafiz Md. Hasan Babu: Logic Synthesis and Minimization of Multiple-Valued Input TANT Networks. The Dhaka University Journal of Science, ISSN: 1022-2502. 56(1): 05-10 (2008)
            46. Hafiz Md. Hasan Babu, Md. Saiful Islam, Md. Rafiqul Islam, Lafifa Jamal, Muhammad Rezaul Karim, Abdullah Al Mahmud: Building Toffoli Network for Reversible Logic Synthesis Based on Swapping Bit Strings. The Dhaka University Journal of Science. 55(2): 153-156 (2007)
            47. Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury: Design of a Compact Reversible Binary Coded Decimal Adder Circuit. Elsevier Journal of Systems Architecture. 52: 272-282 (2006)
            48. Ahsan Raja Chowdhury, Rumana Nazmul , Hafiz Md. Hasan Babu: A New Approach to synthesize Multiple-Output Functions Using Reversible Programmable Logic Array. 19th IEEE International Conference on VLSI Design, Hyderabad, India. 311-316 (2006)
            49. Hafiz Md. Hasan Babu, Abdur Rahim Mustafa, Md. Sumon Shahriar, Lafifa Jamal, Mohammad Hamidullah Ahmad: An Improved Approach of Minimization of Multi-Valued Multi-Output Logic Expressions. The Dhaka University Journal of Science. 54(2): 141-144 (2006)
            50. Hafiz Md. Hasan Babu, et al: Reversible Logic Decomposition to Minimize Full-Adder Circuit. The Dhaka University Journal of Science, ISSN: 1022-2502. 54(2): 137-139 (2006)
            51. Hafiz Md. Hasan Babu, Moinul Islam Zaber: An Approach to Minimize the Multiple-Valued Input Binary-Valued Output functions Using Local Covering. Weases Transaction on Computers, Greece. 10(2): 2381-2389 (2006)
            52. Hafiz Md. Hasan Babu, Tanzeem Iqbal, Chowdhury Farhan Ahmed, Raquibul Hasan, Moinul Islam Zaber, Lafifa Jamal, Shahed Anwar, Mohammad Hamidullah Ahmad: An Optimal Design Method of a Multi-Valued PLA. The Dhaka University Journal of Science. 54(2): 149-152 (2006)
            53. Hafiz Md. Hasan Babu, et al: An Improved Method for Minimization of Circuit Using TANT Network. The Dhaka University Journal of Science, ISSN: 1022-2502. 54(1): 49-54 (2006)
            54. Hafiz Md. Hasan Babu: Realization of Digital Fuzzy Operations Using Multi-Valued Fredkin Gates. International Conference on Computer Design and Conference in Computing in Nanotechnology (CDES’06), Las Vegas, Nevada, USA. 101-106 (2006)
            55. Hafiz Md. Hasan Babu, Amin Ahsan Ali: Design of reversible systolic arrays for digital fuzzy operations. IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan. (2005)
            56. Hafiz Md. Hasan Babu: Design of a Reversible Binary Coded Decimal Adder Using Reversible 4-bit Parallel Adder. 18th IEEE International Conference on VLSI Design, Calcutta, India. 255-260 (2005)
            57. Hafiz Md. Hasan Babu, Md. Sumon Shahriar: An Advanced Minimization Technique for Multiple Valued Multiple Output Logic Expressions using LUT and its Realization using Current Mode CMOS. 8th Euromicro Conference on Digital System Design (DSD’2005), Porto, Portugal. (2005)
            58. Hafiz Md. Hasan Babu, Md. Rafiqul Islam, et. al.: Synthesis of Full-Adder Circuit using Reversible Logic. The 17th International Conference on VLSI Design, Mumbai, India. 757-760 (2004)
            59. Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Moinul Islam Zaber, Md. Mazder Rahman: On the minimization of multiple-valued input binary-valued output functions. 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), Toronto, Canada. 321-326 (2004)
            60. Hafiz Md. Hasan Babu, Md. Rafiqul Islam, et. al: A heuristic approach to synthesize Boolean functions using TANT network. IEEE International Symposium on Circuits and Systems (ISCAS 2004), Vancouver, British Columbia, Canada, VLSI-L7.4. II: 373 – 376 (2004)
            61. Hafiz Md. Hasan Babu, Islam Zaber, Md. Mazder Rahman , Md. Rafiqul Islam: Implementation of multiple-valued flip-flops using pass transistor logic. The IEEE EUROMICRO Symposium on Digital Systems Design (DSD 2004), Rennes, France. (2004)
            62. Hafiz Md. Hasan Babu, Md. Rafiqul Islam, et. al: An improved technique to minimize multiple-output switching functions. The International Conference on Computer Science, Software Engineering, Information Technology, e-Business, and Applications (CSITeA-2003), Brazil. 366-371 (2003)
            63. Md. Rafiqul Islam, Hafiz Md. Hasan Babu: An improved algorithm for query optimization using materialized view. The Dhaka University Journal of Science. (2003)
            64. Hafiz Md. Hasan Babu, Md. Rafiqul Islam , Amin Ahsan Ali: A technique for logic design of voltage-mode pass transistor-based multi-valued multiple-output logic circuits. The IEEE International Conference on Multiple-Valued Logic, Japan. 111-116 (2003)
            65. Hafiz Md. Hasan Babu, Md. Rafiqul Islam, et. al.: A Technique to design minimized multi-valued multi-output logic circuits using pass transistor logic. Proc. of The Work in Progress Session held in Connection with the IEEE EUROMICRO Symposium on Digital Systems Design (DSD 2003), Turkey. 1-2 (2003)
            66. Md. Rafiqul Islam, Hafiz Md. Hasan Babu: A hybrid approach for efficient shortest path algorithm in neural networks. The Dhaka University Journal of Science. (2003)
            67. Hafiz Md. Hasan Babu, Md. Rafiqul Islam, et. al. : Pass transistor logic circuit based on binary decision diagram for characteristic functions of n-bit adder. th International Conference on Computer and Information Technology (ICCIT 2003), Dhaka, Bangladesh. 894-896 (2003)
            68. Md. Rafiqul Islam, Hafiz Md. Hasan Babu, et. al.: A heuristic approach for design for testability of PLAs using pass transistor logic. The twelfth Asian Test Symposium (ATS 2003), China. 90-93 (2003)
            69. Hafiz Md. Hasan Babu, Ahmedul Kabir, A.S.M. Fazle Rabbi: On the modified technique for better data compression. Bangladesh Journal of Scientific and Industrial Research (BJSIR). (2003)
            70. Hafiz Md. Hasan Babu, et. al.: On the Realization of Reversible Full-Adder Circuit. 6th International Conference on Computer and Information Technology (ICCIT 2003), Dhaka, Bangladesh. 2: 880-883 (2003)
            71. Hafiz Md. Hasan Babu, Md. Rafiqul Islam, et. al.: Reversible Logic Synthesis for minimization of Full-Adder Circuit. The IEEE EUROMICRO Symposium on Digital Systems Design (DSD 2003), Turkey. 50-54 (2003)
            72. Hafiz Md. Hasan Babu, Md. Rafiqul Islam: Minimization of multilevel AND-EXOR expressions using Pseudo-Kronecker decision diagrams. The Dhaka University Journal of Science. (2003)
            73. Hafiz Md. Hasan Babu, et. al.: Logic Synthesis and Minimization of Boolean Functions Using TANT Network. 6th International Conference on Computer and Information Technology (ICCIT 2003), Dhaka, Bangladesh. 2: 884-889 (2003)
            74. Md. Rafiqul Islam , Hafiz Md. Hasan Babu: An improved technique to create lattice index of materialized views for query optimization. The Dhaka University Journal of Science. (2003)
            75. Md. Sheikh Sadi, Chowdhury Mofizur Rahman, Hafiz Md. Hasan Babu: An efficient and coherent method using data mining to cluster web documents. The Second International Conference on Computer and Electrical Engineering (ICECE 2002), Dhaka, Bangladesh . (2002)
            76. Hafiz Md. Hasan Babu, T. Sasao: Upper bound on the size of the shared binary decision diagram for an n-bit adder. Journal of Bangladesh Academy of Sciences. 26(1): 119-121 (2002)
            77. Shaily Kabir, M. Karim, Hafiz Md. Hasan Babu: The use of optimal ordering of input variables for simplification of single-output logic functions. The Dhaka University Journal of Science. 50(2): 101-108 (2002)
            78. Md. Shahid Alamgir, Md. Ashraful Islam, Shakila Rahman, Qurratul Aine , Hafiz Md. Hasan Babu: An efficient method to design PLA's for multiple-output functions. The Second International Conference on Computer and Electrical Engineering (ICECE 2002), Dhaka, Bangladesh . (2002)
            79. Hafiz Md. Hasan Babu, M.L. Rahman: Multiple-valued pseudo-Kronecker decision diagrams: A compact representation of multiple-output functions. The Dhaka University Journal of Science. 50(2): 187-196 (2002)
            80. Shaily Kabir, Mahmud Karim, Hafiz Md. Hasan Babu: A heuristic method for simplification of single-output logic functions using optimal ordering of input variables. The Second International Conference on Computer and Electrical Engineering (ICECE 2002), Dhaka, Bangladesh. (2002)

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